Semiconductor package substrates couple semiconductor dies to external circuits, systems, or devices. The semiconductor package substrate typically includes numerous, relatively small, solder bumps or similar conductive structures on the “top” of the substrate to which the semiconductor dies and other components may couple and numerous, relatively large, conductive pads on the “bottom” of the substrate which are used to couple the package to external circuitry. Each of the solder bumps may be conductively coupled to a conductive pad using traces and/or vias formed in the layered semiconductor package substrate. For example, a semiconductor die containing one or more central processing units (“CPUs”) may be coupled to a blade server motherboard using a semiconductor package substrate having a plurality of conductive elements. These conductive elements have a multitude of uses including grounding, power supply, and input/output (I/O) communication.
As CPU clock speeds increase, a demand arises for commensurate increases in communication speed between the CPU and external devices, such as I/O devices, to make full use of the computational power and speed of such processors. To reliably maintain high-speed I/O signals, it is desirable to match the impedance of the semiconductor package coupled to the substrate to external wiring and/or devices. The relatively large conductive pads used to couple the substrate to an external device or system demonstrate considerable capacitance and relatively low inductance, creating an impedance discontinuity between the semiconductor package and the external device or system. This impedance discontinuity restricts signaling bandwidth to and from the CPU and detrimentally limits the computing performance of the system.
Although the following Detailed Description will proceed with reference being made to illustrative embodiments, many alternatives, modifications and variations thereof will be apparent to those skilled in the art.